Senior Design Verification Engineer

For Karachi/Lahore/ Islamabad Office

Job Summary:

We are seeking a Senior Verification/Design Engineer to join our team and contribute to the development of high-performance ASIC/FPGA-based designs. The ideal candidate will be responsible for extracting design requirements, developing micro-architecture, writing RTL code, and ensuring verification coverage. This role offers an exciting opportunity to work with cutting-edge semiconductor technologies and collaborate with industry experts.
Key Responsibilities:

Design Responsibilities:

Extract design requirements from specifications and translate them into architecture, micro-architecture, and RTL design.
Develop and optimize RTL (Register Transfer Level) designs in Verilog/SystemVerilog for ASIC/FPGA-based projects.
Perform unit-level testing on the RTL function and support the verification team by writing self-checking tests.
Work closely with the physical design team to support design integration activities, including linting, CDC, SDC, synthesis, and ECOs.
Collaborate on timing constraints, STA, back annotation of parasitics, gate-level simulations, and equivalence checking.
Perform FPGA emulation and prototyping where required.
Support low-power design methodologies to optimize performance and power efficiency.
Verification Responsibilities:

Work closely with the verification team to review specifications, understand SoC/Core architecture, and define test plans, methodology, and test benches.
Create and execute verification plans based on design specifications.
Develop UVM-based testbenches and implement directed/random test strategies.
Apply constrained random verification methodologies and ensure functional coverage and code coverage.
Debug and resolve issues at simulation and emulation levels.
Perform formal verification and functional equivalence checking.
Required Skills & Qualifications:

B.S. or M.S. in Electrical, Electronics, Computer Engineering, or Computer Science.
2-5+ years of experience in digital design, RTL coding in Verilog/SystemVerilog, and functional verification.
Strong knowledge of CPU architectures (RISC-V, ARM), IP/subsystems, interconnects, and industry-standard interfaces (AMBA, Tile Link, NoCs, etc.).
Understanding of digital design flow, including RTL simulation, logic synthesis, timing constraints (SDC), STA, and power optimization.
Hands-on experience in EDA tools for simulation, synthesis, and verification (Cadence, Synopsys, Mentor Graphics, or equivalent).
Experience in writing scripts using Python, Perl, Tcl, or Shell scripting for automation.
Familiarity with FPGA-based prototyping and low-level system programming in C/C++/assembly is a plus.
Strong problem-solving and analytical skills.
Excellent oral and written communication skills in English.
Strong interpersonal skills and the desire to take on diverse challenges.